Generally, semiconductor memories are categorized into volatile memories that lose data when power is turned off and nonvolatile memories that maintain data even when power is turned off. The nonvolatile memories include EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically EPROMs) and flash EEPROMs. Flash EEPROMs, developed form of conventional EEPROMs, have both an advantage of small cell-size, which is the feature of conventional EPROM and an advantage of being electrically erased, which is the feature of EEPROM. Therefore, the demand for flash EEPROM devices is increasing in the industries.
Flash EEPROM devices are classified into NAND-type flash EEPROM devices and NOR-type flash EEPROM devices according to memory logic array architecture including unit cells. The unit cell of flash EEPROM devices includes a source and a drain formed on a substrate, and a stack-gate which is formed between the source and the drain, and composed of a floating gate and a control gate.
FIG. 1 is a schematic circuit diagram of a conventional NAND-type flash EEPROM device. As shown in FIG. 1, the NAND-type flash EEPROM device is constructed with a plurality of memory strings, a plurality of bit lines BL1 and BL2 and a plurality of word lines WL1, WL2, . . . , WL15 and WL16 which intersect the bit lines BL1 and BL2. Each memory string includes a plurality of unit cells MCa connected in series, a first selection transistor DST serially connected to the first unit cell of the plurality of unit cells and also connected to a bit line BL1 or BL2 and the second selection transistor SST serially connected to the last unit cell of the plurality of unit cells and also connected to a common source line SL. Each unit cell MCa of the memory string is connected to the respective word line WL1, WL2, . . . , WL15 or WL16, the gate of the first selection transistor DST is connected to a drain selection line DSL, and the gate of the second selection transistor SST is connected to a source selection line SSL.
FIG. 2a is a plan layout for illustrating the unit cell structure of the NAND-type flash EEPROM device shown in FIG. 1, and FIG. 2b and FIG. 2c are cross-sectional views taken on line I—I (channel direction) and line II—II (word line direction) of FIG. 2a, respectively. As shown in FIGS. 2a-2c, a source 12 and a drain 13 are formed in the active region of a substrate 11, and a stack gate consisting of a tunnel oxide 14, a floating gate 15, an dielectric layer 16 and a control gate 17 is formed on a channel between the source 12 and the drain 13. An insulating interlayer 18 covers the stack gate and the substrate 11. The plurality of bit line layers 19 are formed in parallel with the memory strings on the insulating interlayer 18. The plurality of word line layers (not shown) are formed in parallel with the control gate 17, and in perpendicular with the bit line layers 19. Also, as most apparently shown in FIG. 2c, the unit cells MCa in the word line direction are electrically separated from the adjacent unit cells MCa by a field oxide layer 20, and the width 20a between the field oxide layers 20 corresponds to the width of the active region.
In the conventional unit cell MCa of the flash EEPROM, the width d of the floating gate 15 is larger than the width 20a of the active region, and thus the floating gate 15 partially overlaps the field oxide layer 20 to increase a gate coupling ratio (GCR). The GCR is important in determining the operating voltage of the unit cell, and can be expressed by the following equation.                     GCR        =                  C1                      C1            +            C2                                              [                  Equation          ⁢                                           ⁢          1                ]            
In equation 1, C1 represents a capacitance between the floating gate 15 and the control gate 17, and C2 represents a capacitance between the floating gate 15 and the substrate 11. Capacitance is proportional to the dielectric constant and the area of a dielectric layer and is inversely proportional to the thickness of the dielectric layer.
In order to reduce the control voltage for programming or erasing data in the unit cell Mca, the GCR value should be increased. Referring to Equation 1 and FIG. 2C, the GCR value can be increased by increasing the dielectric constant of the dielectric layer 16 between the floating gate 15 and the control gate 17, by reducing the thickness of the dielectric layer 16, or by increasing the overlapping area of the control gate 17 and the floating gate 15. However, the first method is difficult to realize because this method needs a new dielectric material. The second method is also difficult to realize because the dielectric layer 16 should insulate the control gate 17 and the floating gate 15 even when a high voltage is applied to the control gate 17 and the floating gate 15 in the programming mode and the erase mode of the unit cell. Therefore, the third method has been mainly used to increase the GCR value. For example, as shown in FIG. 2c, the floating gate 15 extends over the field oxide layer 20 so that overlapping area of control gate 17 and the floating gate 15 increases. In this case, the width t of the cell isolation region is smaller than the width 20b of the field oxide layer 20. Accordingly, though the isolation region having the minimum width t can be produced with an up-to-date photo process equipment, the width 20b of the field oxide layer 20 must be larger than the minimum width t of the isolation region in order to increase the GCR value. Due to the overlap of the floating gate 15 and the field oxide layer 20, the unit cell cannot be produced to have the minimum size, which raises the manufacturing cost of the flash EEPROM device, and also becomes an obstacle in developing a high-density flash EEPROM device.
As other method for decreasing the distance between the active regions, polysilicon spacers can be employed in the unit cell structure of the flash EEPROM device. However, the distance between the active regions cannot be minimized even though the polysilicon spacer is used. In addition, this method has drawbacks in that it requires additional processes to form the polysilicon spacers, and a high manufacturing cost in producing the flash EEPROM devices. The above-mentioned problems are also shown in the NOR-type flash EEPROM devices because the NOR-type flash EEPROM devices also uses the unit cell having the same structure with that of the NAND-type flash EEPROM devices.